Peripheral 8051
System on a Chip

[ P-51 Airplane Image ]

The P-51 "Peripheral 8051" is a new concept: An 8051 with built-in (E)ISA or PC-104 interface and supporting subsystems. These include downloadable Code RAM, dual port RAM, and all eleven IRQs to the host. Unlike classical 8051s, the P-51 naturally and easily interfaces to a host through simple standard buses, and its microsecond timing can provide real-time response to Windows applications.

P-51 Features

All 8051/52 resources:

  • 8K bytes downloadable Code RAM.
  • 256 bytes internal Data RAM.
  • Timers 0, 1, and 2.
  • Ports 0, 1, 2, and 3.
  • All 8051 instructions.
  • All 8051-equivalent Pins.
  • Download Code RAM while reset.
  • Execute Code when released.

[ P-51 Architecture Block Diagram ]

 

EISA/PC-104 interface:

  • 45 EISA signals supported.
  • Uses one of 11 IRQ pins.
  • Software selectable IRQ 3-15.
  • 20 ISA Address pins.
  • 8 ISA Data Bus pins.
  • Hardware or software Reset.
  • Select Segment Addr 0 and A400 to EC00.
  • Uses 16K bytes of system memory space, normally in an Upper Memory Block.

 

Special Features:

  • 4K-byte dual port RAM shared by host and P-51.
  • Dual Data Pointer.
  • Square Root function.
  • Debug capability.
  • Breakpoint and single-step.
  • Software interrupt generation.
  • 3.3v 100-pin QFP.
  • 5v I/O tolerant.
  • 51 MHz operation

 

P-51 Pinout diagram:

 

 

P-51 Package Dimensions:

 

P-51 PCB Pattern:

 

More information is available in our on-line-viewable User Manual or downloadable PDF manual.