CY233 Pinouts

CY233 DIP Pinout
CY233/J PLCC Pinout
CY233/Q QFP Pinout*

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CY233 Dip Pin#	CY233/J PLCC Pin#	CY233/Q QFP* Pin#	Pin Name	I/O	Description
-	1	39	NC		no internal connection
1	2	40	A0	I/O	Parallel device address bit 0, LSB
2	3	41	A1	I/O	Parallel device address bit 1
3	4	42	A2	I/O	Parallel device address bit 2
4	5	43	A3	I/O	Parallel device address bit 3
5	6	44	A4	I/O	Parallel device address bit 4
6	7	1	A5	I/O	Parallel device address bit 5
7	8	2	A6	I/O	Parallel device address bit 6
8	9	3	A7	I/O	Parallel device address bit 7
9	10	4	Reset	I	CY233 hardware reset when high
10	11	5	RxD	I	Received Serial Data into CY233
-	12	6	NC		no internal connection
11	13	7	TxD	O	Transmitted Serial Data from CY233
12	14	5	FPL/	I	Forced parallel load
13	15	9	ACK/	I	Acknowledge of parallel transfer
14	16	10	DAV/	I/O	Data available to parallel device
15	17	11	R-W/	I/O	Read/Write selection for transfer
16	18	12	WR/	I/O	Parallel Write Strobe
17	19	13	RD/	I/O	Parallel Read Strobe or alternate select
18	20	14	Xtal2	I	Crystal oscillator connection
19	21	15	Xtal1	I	Crystal oscillator connection
20	22	16	Vss	I	Ground connection for CY233
-	23	17	NC		no internal connection
21	24	18	DUP	I	Duplex mode selection
22	25	19	NET	I	Network mode selection
23	26	20	U-E-D/	I	Address coding mode selection
24	27	21	CHAR	I/O	Character mode selection
25	28	22	PAR0	I	Parity/Data length selection, LSB
26	29	23	PAR1	I	Parity/Data length selection, MSB
27	30	24	BDR0	I	Baud rate selection, LSB
28	31	25	BDR1	O	Baud rate selection, MSB
29	32	26	ADDR/	O	Address strobe for parallel device
30	33	27	CLK	O	Clock output, 1/6 crystal rate
-	34	28	NC		no internal connection
31	35	29	Test	I	Internal test signal, connect to Vcc
32	36	30	D 7	I/O	Parallel Data Bus bit 7 (MSB)
33	37	31	D 6	I/O	Parallel Data Bus bit 6
34	38	32	D 5	I/O	Parallel Data Bus bit 5
35	39	33	D 4	I/O	Parallel Data Bus bit 4
36	40	34	D 3	I/O	Parallel Data Bus bit 3
37	41	35	D 2	I/O	Parallel Data Bus bit 2
38	42	36	D 1	I/O	Parallel Data Bus bit 1
39	43	37	D 0	I/O	Parallel Data Bus bit 0 (LSB)
40	44	38	Vcc (+ 5V)	I	+5 volt power supply

* QFP Notes:
- While the numbering scheme of the QFP pinout differs from the PLCC, the physical location of functional pins will be identical on both packages.
- The QFP package is currently only available in 1000 quantity minimums.

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Pin Descriptions

Some pin descriptions below show three possible states, TTL 0, TTL 1, or floating (F). Also, many pins on the CY233 are bi-directional, assuming various functions in the different operating modes of the device.

DIP   
Pin#          Mnemonic            Function 
1.  (I/O)        A0              Parallel device address bit 0, LSB
2.  (I/O)        A1              Parallel device address bit 1, 
3.  (I/O)        A2              Parallel device address bit 2, 
4.  (I/O)        A3              Parallel device address bit 3, 
5.  (I/O)        A4              Parallel device address bit 4, 
6.  (I/O)        A5              Parallel device address bit 5, 
7.  (I/O)        A6              Parallel device address bit 6, 
8.  (I/O)        A7              Parallel device address bit 7, MSB
        These pins specify the current address to the parallel 
        device. They are used for address generation and testing.

9.  (I)          Restart         CY233 hardware reset
        The CY233 is hardware rest by this active high signal.

10. (I)          RxD             Received serial data into CY233
        TTL level serial data input to the CY233 through this pin.

11. (O)          TxD             Transmitted serial data into CY233
        TTL level serial data is output on this pin.

12. (I)          FPL/            Forced parallel load
        The local parallel device can force a multi-byte read or
        parallel command operation using this pin.  The read 
        address must also be supplied.

13. (I)          ACK/            Acknowledge of parallel transfer
14. (I/O)        DAV/            Data available to parallel device
15. (I/O)        R-W/            Read/Write selection for transfer
        These pins are used for handshake control of parallel data 
        transfers,indicating when data are stable and have been   
        accepted by the CY233 and local parallel device.

16. (I/O)        WR/             Parallel write strobe for Bus Enable
17. (I/O)        RD/             Parallel read strobe or alternate select
        As an alternative to the handshake data transfers, the CY233
        also supports strobed transfers.  These pins control the timing
        of the transfers in the strobed mode.  Alternate functions are
        available in the handshake mode.

18. (I)          XTAL2           Crystal connection
19. (I)          XTAL1           Crystal connection
        An external 11 MHz crystal or clock source is connected to these
        pins. All baud rates and device timing are derived from this 
        clock.

20. (I)          VSS             Power supply common

21. (I)          DUP             Duplex mode selection
22. (I)          NET             Network mode selection
        Select the communications mode through these pins.

        NET DUP ECHO        MODE        USEFUL FOR
        0   0   Invalid     Master      Ring Network
        0   F   None        Master      Point to Point
        0   1   All         Master      Ring Network
        F   0   Invalid     Slave       Ring Network
        F   F   None        Slave       Half Dup. Line Turnaround
        F   1   All         Slave       Console to CY233
        1   0   Valid       Master      Console to CY233
        1   F   Valid       Slave       Bus
        1   1   Valid       Slave       Bus

23. (I)          U-E-D/          Address coding mode selection
        Select the CY233 addressing format through this pin.

        1       Uncoded UART mode, addresses not used
        F       Encoded Address, positive true binary
        0       Decoded Address, negative true, 1 of 8

24. (I/O)        CHAR            Character mode selection
        This pin selects the data representation for the contents of
        serial messages.  When the CY233 is running, it may also be
        used to enable tri-state transmit drivers.

                 F       ASCII Character mode
                 1       ASCII Hexadecimal character mode
                 0       Binary Character mode

25. (I)          PAR0            Parity/Data length selection, LSB
26. (I)          PAR1            Parity/Data length selection, MSB
        Select parity and character length options with these pins.

                                  Data      Total Character
            PAR1 PAR0  Parity     Length    Length

            F    F     Mark       7         10
            F    1     Even       7         10
            F    0     Odd        7         10
            1    F     Space      7         10
            1    1     None       8         10
            1    0     Space      8         11
            0    F     Mark       8         11
            0    1     Even       8         11
            0    0     Odd        8         11

27. (I)          BDR0           Baud rate selection, LSB
28. (I)          BDR1           Baud rate selection, MSB
        These pins select the CY233 baud rate as follows:

                 BDR1 BDR0      Rate with 11.059 MHz clock
                 F    F         Self Adaptive
                 F    1         57600
                 F    0         19200
                 1    F         9600
                 1    1         4800
                 1    0         2400
                 0    F         1200
                 0    1         600
                 0    0         300

29. (O)          ADDR/           Address strobe for parallel device
        A short strobe is generated on this line when the CY233 has
        written a new address to lines A0-A7, but before the lines
        are tested. Could be used to trigger external addressing logic.

30. (O)          CLK             Clock output, 1/6 crystal rate
31. (I)          TEST            Internal test signal, connect to Vcc

32. (I/O)        D7              Parallel data bit 7, MSB
33. (I/O)        D6              Parallel data bit 6
34. (I/O)        D5              Parallel data bit 5
35. (I/O)        D4              Parallel data bit 4
36. (I/O)        D3              Parallel data bit 3
37. (I/O)        D2              Parallel data bit 2
38. (I/O)        D1              Parallel data bit 1
39. (I/O)        D0              Parallel data bit 0, LSB
        These bi-directional lines are used for all parallel data
        transfers between the CY233 and local parallel devices.

40. (I)          VCC             +5 Volt power supply

** The CY233 and the CY232 are NOT pin compatible. The CY233 contains all the features of the CY232, and is recommended in place of the CY232 for new designs.